One common type of memory cell includes a pair of NPN bipolar transistors arranged in a cross-coupled configuration for reading (i.e. storing) and writing a pair of binary data signals responsive to selected enable signals. In one configuration, such a memory cell includes a PNP transistor connected as a load to each of the cross-coupled transistors, and various read/write access transistors or buffering data into and out of the cell.
Such memory cells typically constitute a compromise of well-known operational parameters including, but not limited to: minimizing standby current and total current requirements, maximizing the speed of various read/write operations, and minimizing the likelihood of errors in the read/write data.
Many such memory cell configurations are known in the art, several of which are briefly referenced below.
J. R. Cavaliere et al., "Bipolar Random-Access Memory Cell with Bilateral NPN Bit Line Coupling Transistors", IBM Technical Disclosure Bulletin, Vol. 20, No. 4, September 1977, pages 1447-1450 shows several configurations of the above-described memory cell wherein PNP transistors are connected in the typical manner as passive load elements for the cross-coupled transistor pair.
U.S. Pat. No. 3,643,235 to Berger et al. (assigned to the assignee of the present invention) shows a similar memory cell (see particularly FIGS. 4 and 8) wherein the bias characteristics of the PNP load transistors are adjustable to control the supply of the current to the cross-coupled transistors. The Berger et al. circuits suffer from the disadvantage that the operation of the load transistors is synchronized to the operation of the bit lines in a manner that would tend to impede the rapid writing of the cell. Further, the load transistors in the FIG. 8 embodiment operate in a saturated mode that would tend to further impede the rapid operation of the cell.
U.S. Pat. 4,228,525 to Kawarada et al. shows a memory cell of the type described above, i.e. with cross-coupled NPN storage transistors having PNP loads, wherein the bases of the load transistors are connected to a bulk, buried word line. This circuit suffers from the disadvantage of having the load transistors operate in a relatively uncontrolled manner which is not optimal to the operation of the memory cell.
In this field of art, any memory cell which optimizes the desirable operating characteristics of a memory cell, such as fast, low power operation, while minimizing undesirable characteristics, such as soft error rates, represents a substantial contribution to the art.